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How to ensure PCB design signal integrity?

Time:2021-06-21 14:58

Signal Integrity (SI) refers to the quality of the signal on the signal line, i.e., the ability of the signal to respond in the circuit with the correct timing and voltage.
If the signal in the circuit can reach the receiver with the required timing, duration and voltage amplitude, the circuit can be determined to have good signal integrity.
Conversely, a signal integrity problem occurs when the signal does not respond properly.
With the use of high-speed devices and the increasing number of high-speed digital system designs, system data rates, clock rates, and circuit densities are increasing.
In such designs, where system fast-slope transients and operating frequencies are high, cables, interconnects, printed boards (PCBs), and silicon will exhibit very different behavior from low-speed designs, i.e., signal integrity issues arise.
Signal integrity issues can cause or directly bring about such things as signal distortion, timing errors, incorrect data, address, control line and system errors, and even crash the system, which has become a very noteworthy issue in high-speed product design.
This paper first introduces the issue of PCB signal integrity, followed by a description of the steps of PCB signal integrity, and finally describes how to ensure the signal integrity of PCB design.
 
PCB signal integrity issues
PCB signal integrity issues mainly include signal reflection, crosstalk, signal delay and timing errors.
1, reflection: signal transmission on the transmission line, when the characteristic impedance of the transmission line on the high-speed PCB and the signal source impedance or load impedance mismatch, the signal will be reflected, so that the signal waveform overshoot, undershoot and the resulting ringing phenomenon.
Overshoot (Overshoot) is the first peak (or valley) of a signal jump, which is an additional voltage effect above the power supply level or below the reference ground level.
Undershoot (Undershoot) is the next valley (or peak) of the signal jump.
Excessive overshoot voltage often long-term impact will cause damage to the device, down-shoot will reduce the noise tolerance, ringing increases the time required for signal stabilization, thus affecting the system timing.
 
2, crosstalk: In the PCB, crosstalk is when the signal propagates on the transmission line, due to electromagnetic energy through mutual capacitance and mutual inductance coupling on adjacent transmission lines produce undesired noise interference.
It is generated by the interaction of electromagnetic fields caused by different structures in the same area. Mutual capacitance triggers coupling currents, known as capacitive crosstalk.
And mutual inductance triggers coupling voltage, known as inductive crosstalk. On the PCB, crosstalk and alignment length, signal line spacing, and the condition of the reference ground plane.
 
3, signal delay and timing errors: the signal is transmitted at a finite speed on the PCB's wire, the signal is sent from the driver side to the receiver side, during which there is a transmission delay.
Excessive signal delay or signal delay mismatch may lead to timing errors and logic device function confusion.
High-speed digital system design analysis based on signal integrity analysis can not only effectively improve product performance, but also shorten product development cycle and reduce development cost.
In the development of digital systems to high-speed, high-density direction, mastering this design tool is very urgent and necessary.
In the signal integrity analysis model and computational analysis algorithms continue to improve and improve, the use of signal integrity for computer design and analysis of digital system design methods will be very extensive, very comprehensive application.
 
PCB signal integrity steps
 
1、Pre-design preparation
Before the design begins, you must first think about and determine the design strategy, so as to guide such work as the selection of components, process selection and board production cost control.
In terms of SI, research should be conducted in advance to form a planning or design guidelines to ensure that the design results do not appear obvious SI problems, crosstalk or timing problems.
 
2, the board's lamination
Some project teams have a lot of autonomy in determining the number of PCB layers, while others do not have such autonomy, so it is important to understand where you are.
Other important questions include: What are the expected manufacturing tolerances? What is the expected insulation constant on the board? What is the allowable error in line width and spacing? What are the allowable tolerances for the thickness and spacing of the ground and signal layers? All this information can be used in the pre-wiring phase.
Based on the above data, you can then choose the layer stack. Note that almost every PCB inserted into another board or backplane has a thickness requirement, and most board manufacturers have fixed thickness requirements for the different types of layers they can manufacture, which will greatly constrain the number of final laminates.
You may be tempted to work closely with the manufacturer to define the number of layers. Impedance control tools should be used to generate target impedance ranges for the different layers, making sure to take into account the manufacturing tolerances provided by the manufacturer and the effects of adjacent wiring.
Ideally, with signal integrity, all high-speed nodes should be wired on the inner impedance control layer (e.g., ribbon lines).
To optimize SI and keep the board decoupled, ground/power layers should be placed in pairs whenever possible. If you can only have a pair of ground/power layers, you'll just have to make do.
If there is no power supply layer at all, by definition you may run into SI problems. You may also encounter the situation that it is difficult to simulate or emulate the performance of the board before the return path of the signal is not defined.
 
3, crosstalk and impedance control
Coupling from adjacent signal lines will cause crosstalk and change the impedance of the signal line. Coupling analysis of adjacent parallel signal lines may determine the "safe" or expected spacing (or parallel wiring length) between signal lines or between various types of signal lines.
For example, if you want to limit crosstalk from the clock to the data signal node to 100mV or less, but want the signal alignments to remain parallel, you can find the minimum allowable spacing between signals on any given wiring layer through calculation or simulation.
Also, if the design contains nodes with important impedance (or clock or dedicated high-speed memory architecture), you will have to place the wiring on a layer (or layers) to get the desired impedance.
 
4. Significant high-speed nodes
Latency and time lag are key factors that must be considered for clock cabling. Because of the strict timing requirements, such nodes must usually be terminated to achieve the best SI quality.
To pre-determine these nodes, while the time required to adjust component placement and wiring is planned in order to adjust the signal integrity design pointers.
 
5, technology selection
Different drive technologies are suitable for different tasks. Is the signal point-to-point or point-to-multi-tap? The signal is output from the board or stay on the same board? What is the allowed time lag and noise margin?
As a general guideline for signal integrity design, the slower the conversion speed, the better the signal integrity. there is no reason to use a 500PS rise time for a 50MHZ clock.
A 2-3NS swing rate control device needs to be fast enough to ensure SI quality and help solve problems like synchronous switching of outputs (SSO) and electromagnetic compatibility (EMC).
The superiority of drive technology can be found in new FPGA programmable technologies or user-defined ASICs. With these custom (or semi-custom) devices, you have a lot of leeway to select the drive amplitude and speed.
Early in the design, meet the FPGA (or ASIC) design time requirements and determine the proper output selection, including pin selection if possible.
During this design phase, obtain the appropriate simulation model from the IC supplier. To effectively cover the SI simulation, you will need an SI simulation program and the appropriate simulation model (possibly an IBIS model).
Finally, in the prewiring and wiring phase you should establish a series of design guidelines, which include: target layer impedance, wiring spacing, preferred device process, important node topology and termination planning.
 
6. Pre-wiring phase
 
The basic process of pre-wiring SI planning is to first define a range of input parameters (drive amplitude, impedance, tracking speed) and a range of possible topologies (min/max length, short length, etc.), then run each possible combination of simulations, analyze timing and SI simulation results, and finally find an acceptable range of values.
Next, the working range is interpreted as a wiring constraint for PCB routing. Different software tools can be used to perform this type of "clean-up" preparation, and the wiring program can handle these wiring constraints automatically.
For most users, timing information is actually more important than SI results, and the results of interconnect simulation can change the wiring and thus adjust the timing of the signal path.
In other applications, this process can be used to determine the layout of pins or devices that are incompatible with the system timing pointer.
In this case, it is possible to completely identify nodes that need to be hand-wired or nodes that do not need to be terminated. For programmable devices and ASICs, the choice of output drivers can also be adjusted at this time to improve the SI design or to avoid discrete terminated devices.
 
7, SI simulation after wiring
In general, SI design guidance rules are difficult to ensure that no SI or timing problems occur after the actual wiring is completed. Even if the design is guided by the guidelines, unless you can continuously and automatically check the design, there is no guarantee that the design will fully comply with the guidelines, and thus problems will inevitably arise.
Post-wiring SI simulation checks will allow for planned breaks (or changes) to the design rules, but this is only necessary for cost reasons or under strict wiring requirements.
 
8, post-manufacturing stage
Take the above measures to ensure the board's SI design quality, after the board is assembled, it is still necessary to put the board on the test platform, using an oscilloscope or TDR (time domain reflectometer) measurements, the real board and simulation of the expected results for comparison.
These measurements can help you improve the model and manufacturing parameters, so that you can make better (less constrained) decisions in the next pre-design research work.
 
9, the choice of models
Much has been written about model selection, and engineers performing static timing verification may have noticed that despite all the data available from device data sheets, it is still difficult to build a model.
SI simulation models are just the opposite; the model is easy to build, but the model data is difficult to obtain. Essentially, the only reliable source of SI model data is the IC supplier, who must work in tacit cooperation with the design engineer.
The IBIS model standard provides a consistent data carrier, but the establishment of IBIS models and their quality assurance is costly, IC suppliers still need to invest in this market demand-driven role, while the board manufacturer may be the only demand-side market.
PCB design methods to ensure signal integrity
 
By summarizing the factors that affect signal integrity, in the PCB design process to better ensure signal integrity, can be considered from the following aspects.
 
1) circuit design considerations. Including control of the number of synchronous switching outputs, control the maximum edge rate of each unit (dI/dt and dV/dt), so as to obtain the lowest and acceptable edge rate; selection of differential signals for high output functional blocks (such as clock drivers).
 
Terminating passive components (e.g., resistors, capacitors, etc.) on the transmission line to achieve impedance matching between the transmission line and the load.
 
2) Minimize the alignment length of parallel wiring.
 
(3) Component placement should be far away from the I/O interconnect interface and other areas susceptible to interference and coupling, and minimize the placement interval between components.
 
(4) shorten the distance between the signal alignment to the reference plane interval.
 
(5) reduce the impedance of the alignment and signal drive level.
 
6)Terminal matching. Can increase the terminal matching circuit or matching components.
 
(7) Avoid parallel wiring, provide sufficient interval between alignments, and reduce inductive coupling.

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